1. Field
The embodiment generally relates to a circuit design method and a circuit design system, in which a power consumption considering an IR-drop can be calculated.
2. Description of the Related Art
Conventionally, in an LSI (Large Scale Integration) design, in a case of supplying power to a chip, it is assumed that the same power supply voltage is applied to all cells arranged on the chip, and power to be consumed is calculated for each cell. By using the calculated power to be consumed, a voltage drop, that is, an IR-drop is calculated based on a resistance value of the power supply of the chip. Also, a voltage decreased due to the IR-drop is calculated for each cell. After that, a simulation including a delay calculation and a timing analysis is performed by using the calculated power to be consumed and the calculated power for each cell after the IR-drop.
However, since the power to be consumed by the chip is calculated in a state in which the IR-drop does not occur and the power decreased due to the IR-drop is calculated, a voltage different between the power to be consumed and the power decreased due to the IR-drop is greater than an actual voltage difference. Accordingly, it is required to guarantee a voltage in a wider range for each cell, and thus, it is demanded to assure excessive timing in a design stage. As a result, a voltage range is guaranteed much more than is actually required, and a chip size and a cost are increased.